Application of big data has a higher requirement for a computer processing capability. An important indicator of improving the computer processing capability is an improvement of a memory capacity. In an application scenario, because of a limited integration level of an existing memory chip, multiple memory chips are connected by using an extension chip, so as to expand the memory capacity. In another application scenario, an application acceleration chip is added to more computer systems to perform acceleration processing on some specific applications. For example, a graphics processing unit (GPU) is usually used for acceleration during processing of graphical and image data. Generally, such an application acceleration chip may be implemented by using an application-specific integrated circuit (ASIC) or an field programmable gate array (FPGA).
The foregoing two application scenarios may be described based on FIG. 1. A processor system 101, a system memory 102, a memory extension chip 103, and an extended memory 104 are included in FIG. 1, and a memory controller 1011 is integrated into the processor system 101. The system memory 102 is connected to the processor system 101 by using a memory bus, the extended memory 104 is connected to the memory extension chip 103 by using the memory bus, and the processor system 101 may be connected to the memory extension chip 103 through the memory controller 1011 in multiple manners.
In a first existing technology, an implementation manner is to use an I/O bus to connect the processor system 101 and the memory extension chip 103. A commonly used I/O bus includes a Peripheral Component Interconnect Express (PCI-E) bus, an Intel Quick Path Interconnect (QPI) bus, or an AMD HyperTransport (HT) bus. By using the I/O bus, there is a relatively high delay, and refined pipeline design is required for the memory extension chip 103, so as to compensate for a data access delay.
In a second existing technology, an implementation manner is to use a memory bus to connect the processor system 101 and the memory extension chip 103. The use of the memory bus enables the memory extension chip 103 and the processor system 101 to directly share the extended memory 104, so that a memory access delay is relatively small.
The technical means in the second existing technology has the following problems: Because there is the memory extension chip 103 between the processor system 101 and the extended memory 104, after the processor system 101 sends a memory access request for accessing data in the extended memory 104, when the integrated memory controller 1011 receives the memory access request and accesses the extended memory 104 by using a double data rate (DDR) protocol, an extra delay is caused by existence of the memory extension chip 103. Consequently, a processing result of the memory access request cannot be returned within a delay required by the DDR protocol, and feasibility of accessing the extended memory 104 by the foregoing computer system is affected.
To resolve the foregoing delay problem, in the prior art, a manner of modifying a time sequence parameter of a memory controller is used, that is, the time sequence parameter of the memory controller integrated into a processor is modified, so that the time sequence parameter of the processor is greater than an actual memory access delay. However, because the processor supports a limited setting range of a maximum time sequence parameter, it is difficult to compensate for an extra access delay in a process of accessing an extended memory.